1. Field of Invention
This invention relates to semiconductor device formation and particularly to the formation of source-drain extension regions.
2. Related Art
One trend of the semiconductor industry is to make semiconductor devices as small as possible. Often, however, process technology or the methods used in forming many devices impose limitations on how small a device can be made.
A typical semiconductor device and a primary building block in the semiconductor industry is the metal oxide semiconductor field effect transistor (MOSFET). A cross-section of a MOSFET is shown in FIG. 1. A MOSFET is typically composed of a gate 120 and an insulating gate oxide layer 115 both formed over a silicon substrate 110. Gate 120 is usually composed of polysilicon. Within substrate 110 are formed deep source-drain regions 150 (sometimes referred to as heavily doped source and drain regions) and source-drain extension regions 130 (sometimes referred to as lightly doped source and drain regions). Generally, doped regions are regions containing a higher concentration of p-type or n-type dopants than the substrate. Source-drain extension regions 130 generally have a lower concentration of dopants compared to deep source-drain regions 150, although some technologies allow the regions to be doped at equivalent levels. Further source-drain extension regions 130 have a thickness t.sub.1 which is smaller than thickness t.sub.2 of deep source-drain regions 150. Shallow source-drain extension regions 130 are important for reducing hot carrier injection (HCI), which often occurs in scaled down (e.g., sub-micron) devices, and for maintaining other device characteristics such as threshold voltage rolloff, punchthrough, and other short channel characteristics. Thicker deep source-drain regions are generally important for lowering device resistivity, for maximizing drive current.
In reducing the size of MOSFET devices much of the focus has been on reducing the length L of the gate 120. As the gate length L is reduced, however, the device size must also be reduced in the vertical direction--that is, the source-drain extension region thickness t.sub.1 must be reduced. Formation of shallow source-drain extension regions, however, requires precise control of dopant distribution on a fine scale. Unfortunately, while technology will allow other portions of MOSFET devices to be scaled smaller, e.g., gates scaled to sub-micron lengths, limitations in forming finely scaled source-drain extension regions have prevented semiconductor devices from reaching their smallest dimensions.
Typically conventional processes of forming a MOSFET device will have the following steps. Gate oxide 115 and gate 120 are formed on substrate 110. Source-drain extension regions 130 are next formed, often by ion implantation. Once source-drain extension regions 130 are formed, oxide spacers are formed abutting the gate 120 to protect the source-drain extension regions from further doping. Deep source-drain regions are then formed, often by ion implantation. These regions (both source-drain extension and deep source-drain) are then annealed by heating to form the proper lattice structures and to electrically activate the dopants in these regions. Before removing the spacers, and usually after annealing, a silicide or other conductive layer is formed on the deep source-drain regions 150 and gate 120 to increase conductivity. Silicidation generally requires two additional heating steps.
There are generally two ways to make a doped region shallower. One way is to implant ions at a lower energy (e.g., 1 keV instead of 20 keV). The second way to reduce the amount of dopant diffusion is to reduce anneal time and/or temperature. Annealing and other heat steps cause the doped regions to diffuse, thus causing the doped regions to expand and deepen in thickness. The longer the time and the higher the temperature of a heat step, the deeper the doped regions become.
In common processes, both deep source-drain and source-drain extension regions are annealed simultaneously, or source-drain extension regions are annealed and then re-exposed to anneal temperatures during the deep source-drain region anneal. These anneal steps cause both types of regions to deepen as a result of diffusion. By annealing for a shorter time or at a lower temperature, the source-drain extension region thickness can be minimized, especially if a low energy implant of the source-drain extension region is also used. Nonetheless, a reduced anneal would also cause the deep source-drain regions to be formed too shallow. Too shallow a deep source-drain region is undesirable because it alters device characteristics (e.g., device resistivity and drive current) and makes formation of reliable contacts difficult. Silicidation of deep source-drain regions eats into the deep source-drain depth, causing an already shallow deep source-drain region to be even further reduced.
Thus, even using a low energy source-drain extension implant with conventional device formation processes, the manufacturer has very limited control over maintaining shallow source-drain extension thickness because of diffusion resulting from subsequent anneal and other heat steps and because deep source-drain depth must be maintained.
Other methods of forming source-drain extension regions have been put forth as allowing more control in the formation of such extension regions. One such method is laser doping. These methods, however, have not been generally used because of serious process problems, including melting the polysilicon gate in the case of laser doping.
Therefore, it is desirable to develop a process which allows for more controlled shallow source-drain extension formation without affecting deep source-drain region depth or negatively influencing other device characteristics.